Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network

Yasuhiro TAKE  Tadahiro KURODA  

IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.4   pp.322-332
Publication Date: 2015/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.322
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
TCI,  Coupled-resonator,  3-D Integration,  3-D clock distribution,  CDR,  

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This paper presents an inductive coupling interface using a relay transmission scheme and a low-skew 3D clock distribution network synchronized with an external reference clock source for 3D chip stacking. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in the elimination of a source-synchronous clock link. As a result, the total number of coils required is reduced to one-fifth of the conventional number required, yielding a significant improvement in data rate, layout area, and energy consumption. A low-skew 3D clock distribution network utilizes vertically coupled LC oscillators and horizontally coupled ring oscillators. The proposed frequency-locking and phase-pulling scheme widens the lock range to ± 10%. Two test chips were designed and fabricated in 0.18 μm CMOS. The bandwidth of the proposed interface using relay transmission ThruChip Interface (TCI) is 2.7 Gb/s/mm2; energy consumption per chip is 0.9 pJ/b/chip. Clock skew is less than 18- and 25- ps under a 1.8- and 0.9- V supply. The distributed RMS jitter is smaller than 1.72 ps.