A Monolithic Sub-sampling PLL based 6–18 GHz Frequency Synthesizer for C, X, Ku Band Communication

Hanchao ZHOU  Ning ZHU  Wei LI  Zibo ZHOU  Ning LI  Junyan REN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.1   pp.16-27
Publication Date: 2015/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.16
Type of Manuscript: PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
sub-sampling,  frequency synthesizer,  phase-locked loop (PLL),  SSB mixer,  injection-locked frequency doubler,  radar system,  

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Summary: 
A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13 μm CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6–18 GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise -113.7 dBc/Hz@100 kHz in the best case and the reference spur is below -60 dBc. The core of the synthesizer consumes about 110 mA*1.2 V.