Delay Defect Diagnosis Methodology Using Path Delay Measurements

Eun Jung JANG  Jaeyong CHUNG  Jacob A. ABRAHAM  

IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.10   pp.991-994
Publication Date: 2015/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.991
Type of Manuscript: BRIEF PAPER
Category: Semiconductor Materials and Devices
VLSI testing,  delay faults,  delay defects,  defect diagnosis,  fault localization,  

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With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.