For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
99.4% Switching Energy Saving and 87.5% Area Reduction Switching Scheme for SAR ADC
Li BIN Deng ZHUN Xie LIANG Xiangliang JIN
IEICE TRANSACTIONS on Electronics
Publication Date: 2015/10/01
Online ISSN: 1745-1353
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
analog-to-digital converter (ADC), successive approximation register (SAR), energy saving,
Full Text: PDF(536.8KB)>>
A high energy-efficiency and area-reduction switching scheme for a low-power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Based on the sequence initialization, monotonic capacitor switching procedure and multiple reference voltages, the average switching energy and total capacitance of the proposed scheme are reduced by 99.4% and 87.5% respectively, compared to the conventional architecture.