Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC

Wenjun ZHAO

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E98-A    No.8    pp.1787-1795
Publication Date: 2015/08/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E98.A.1787
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
fast mode decision,  H.265/HEVC,  hardware architecture,  mode dispatch module,  

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In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.

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