Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization

Jun SHIOMI  Tohru ISHIHARA  Hidetoshi ONODERA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E98-A   No.7   pp.1455-1466
Publication Date: 2015/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E98.A.1455
Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
near-threshold computing,  statistical static timing analysis (SSTA),  

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Summary: 
Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.