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Efficient Algorithm and Fast Hardware Implementation for Multiplyby(1+2^{k})
ChinLong WEY PingChang JUI MuhTian SHIUE
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E98A
No.4
pp.966974 Publication Date: 2015/04/01 Online ISSN: 17451337
DOI: 10.1587/transfun.E98.A.966 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: constant multiplier, ripple carry adder (RCA), carrylookahead adder (CLA), hybrid adder (HyA), booth algorithm,
Full Text: PDF(1.8MB)>>
Summary:
A constant multiplier performs a multiplication of a datainput with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiplyby(1+2^{k}) operation with additions. No multiplications are needed. The value of (1+2^{k})N can be computed by adding N to its kbit leftshifted value 2^{k}N. The additions can be performed by the fulladderbased (FAbased) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCAbased RCA which achieves 35% faster than the FAbased RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.

