1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application

Takashi KAWAMOTO  Masato SUZUKI  Takayuki NOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E98-A    No.2    pp.485-491
Publication Date: 2015/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E98.A.485
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
calibration,  serial ATA,  phase-locked loop (PLL),  spread-spectrum clock generator (SSCG),  

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A serial ATA PHY fabricated in a 0.15-µm CMOS process performs the serial ATA operation in an asynchronous transition by using large variation in the reference clock. This technique calibrates a transmission signal frequency by utilizing the received signal. This is achieved by calibrating the divide ratio of a spread-spectrum clock generator (SSCG). This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400ppm, i.e., higher than the permissible TX frequency variations (i.e., 350ppm). The calibrated transmission signal achieved a total jitter of 3.9ps.