Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor

Ju Hee CHOI  Jong Wook KWAK  Chu Shik JHON  

IEICE TRANSACTIONS on Information and Systems   Vol.E97-D   No.8   pp.2166-2169
Publication Date: 2014/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E97.D.2166
Type of Manuscript: LETTER
Category: Computer System
cache coherence,  non volatile memory,  STT-RAM,  chip multi-processor,  

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Non-Volatile Memories (NVMs) are considered as promising memory technologies for Last-Level Cache (LLC) due to their low leakage and high density. However, NVMs have some drawbacks such as high dynamic energy in modifying NVM cells, long latency for write operation, and limited write endurance. A number of approaches have been proposed to overcome these drawbacks. But very little attention is paid to consider the cache coherency issue. In this letter, we suggest a new cache coherence protocol to reduce the write operations of the LLC. In our protocol, the block data of the LLC is updated only if the cache block is written-back from a private cache, which leads to avoiding useless write operations in the LLC. The simulation results show that our protocol provides 27.1% energy savings and 26.3% lifetime improvements in STT-RAM at maximum.