Fast Implementation of KCipher-2 for Software and Hardware

Yuto NAKANO  Kazuhide FUKUSHIMA  Shinsaku KIYOMOTO  Tsukasa ISHIGURO  Yutaka MIYAKE  Toshiaki TANAKA  Kouichi SAKURAI  

IEICE TRANSACTIONS on Information and Systems   Vol.E97-D   No.1   pp.43-52
Publication Date: 2014/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E97.D.43
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Information Network
stream cipher,  KCipher-2,  software implementation,  hardware implementation,  

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KCipher-2 is a word-oriented stream cipher and an ISO/IEC 18033 standard. It is listed as a CRYPTREC cryptographic algorithm for Japanese governmental use. It consists of two feedback shift registers and a non-linear function. The size of each register in KCipher-2 is 32 bits and the non-linear function mainly applies 32-bit operations. Therefore, it can be efficiently implemented as software. SNOW-family stream ciphers are also word-oriented stream ciphers, and their high performance has already been demonstrated.We propose optimised implementations of KCipher-2 and compare their performance to that of the SNOW-family and other eSTREAM portfolios. The fastest algorithm is SNOW 2.0 and KCipher-2 is the second fastest despite the complicated irregular clocking mechanism. However, KCipher-2 is the fastest of the feasible algorithms, as SNOW 2.0 has been shown to have a security flaw. We also optimise the hardware implementation for the Virtex-5 field-programmable gate array (FPGA) and show two implementations. The first implementation is a rather straightforward optimisation and achieves 16,153 Mbps with 732 slices. In the second implementation, we duplicate the non-linear function using the structural advantage of KCipher-2 and we achieve 17,354 Mbps with 813 slices. Our implementation of KCipher-2 is around three times faster than those of the SNOW-family and efficiency, which is evaluated by “Throughput/Area (Mbps/slice)”, is 3.6-times better than that of SNOW 2.0 and 8.5-times better than that of SNOW 3G. These syntheses are performed using Xilinx ISE version 12.4.