Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Wenpo ZHANG  Kazuteru NAMBA  Hideo ITO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E97-D    No.10    pp.2719-2729
Publication Date: 2014/10/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2014EDP7110
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
small-delay defects,  fault coverage,  segmented scan,  control point,  observation point,  

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Summary: 
With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.


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