New Address Method for Reducing the Address Power Consumption in AC-PDP

Beong-Ha LIM  Gun-Su KIM  Dong-Ho LEE  Heung-Sik TAE  Seok-Hyun LEE  

IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.8   pp.820-827
Publication Date: 2014/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.820
Type of Manuscript: PAPER
Category: Electronic Displays
Address power consumption,  Overlap scan method,  Two-step address voltage,  PDP,  Plasma,  

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This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6 Wh (58%) when compared with the conventional method.