A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation

Rui WU  Yuuki TSUKUI  Ryo MINAMI  Kenichi OKADA  Akira MATSUZAWA  

IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.8   pp.803-812
Publication Date: 2014/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.803
Type of Manuscript: PAPER
Category: Electronic Circuits
60-GHz PA,  HCI issues,  CMOS,  mixed analog-digital LDO,  time division duplex,  

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A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage VPA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.