Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

Satoshi TAKAYA  Hiroaki IKEDA  Makoto NAGATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.6   pp.557-565
Publication Date: 2014/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.557
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
wide I/O bus,  through silicon via,  signal integrity,  power integrity,  

Full Text: FreePDF


Summary: 
A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9mm × 9.9mm die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75V for error free data transfer at 100GByte/sec, achieving the energy efficiency of 0.21pJ/bit.