A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS

Sho IKEDA  Sang_yeop LEE  Tatsuya KAMIMURA  Hiroyuki ITO  Noboru ISHIHARA  Kazuya MASU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.6   pp.495-504
Publication Date: 2014/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.495
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
injection-locked frequency divider,  phase-locked loop,  Class-C VCO,  CMOS,  low supply voltage,  

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Summary: 
This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.