A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Yohei NAKATA  Yuta KIMI  Shunsuke OKUMURA  Jinwook JUNG  Takuya SAWADA  Taku TOSHIKAWA  Makoto NAGATA  Hirofumi NAKANO  Makoto YABUUCHI  Hidehiro FUJIWARA  Koji NII  Hiroyuki KAWAI  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.4   pp.332-341
Publication Date: 2014/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.332
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustness,  cache,  variation tolerance,  7T/14T SRAM,  

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Summary: 
This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.