Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC

Jeong-Gun LEE  Myeong-Hoon OH  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.4   pp.253-263
Publication Date: 2014/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.253
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuit,  FPGA device,  MIPS processor,  low power,  

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Summary: 
A modern system-on-chip (SoC) includes many heterogeneous IP components. Generally, a few embedded processors are integrated into SoCs. An asynchronous circuit design technique is employed to achieve low power/energy consumption. In this paper, we design an asynchronous embedded processor on FPGAs and analyze its possible benefits on commercial FPGAs. We use commercially available 65nm high-performance Virtex-5 and 45nm low-power Spartan-6 Xilinx FPGAs to show the impact on power consumption for the two different extreme cases. For the high performance Virtex-5, our asynchronous processor shows 36.8% lower power consumption when compared with its synchronous counterpart. On the other hand, the asynchronous processor consumes 25.6% more power in a low power Spartan-6 FPGA. However, through simple analysis and power simulation, we show that the event-driven nature of asynchronous circuits can further save power/energy even in the Spartan-6 FPGA.