A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking

Jeong-Gun LEE  

IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.12   pp.1158-1161
Publication Date: 2014/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.1158
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
electromagnetic interference,  EMI,  multi-frequency clocking,  asynchronous circuits,  

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In this paper, we propose a new design technique called asynchronous multi-frequency clocking for suppressing EMI at a chip design level by combining two independent EMI-suppressing approaches: multi-frequency clocking and asynchronous circuit design techniques. To show the effectiveness of our approach, a five-stage pipelined asynchronous MIPS with multi-frequency clocking has been implemented on a commercial Xilinx FPGA device. Our approach shows 11.05 dB and 5.88 dB reductions of peak EM radiation in the prototyped implementation when compared to conventional synchronous and bundled-data asynchronous circuit counterparts, respectively.