Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links

Chang-chun ZHANG  Long MIAO  Kui-ying YIN  Yu-feng GUO  Lei-lei LIU  

IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.11   pp.1104-1111
Publication Date: 2014/11/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.1104
Type of Manuscript: PAPER
Category: Electronic Circuits
CMOS,  serializer,  phase-locked loop,  delay-locked loop,  parallel links,  

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A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-μm CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673 μm×667 μm with a core width of only 450 μm. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8 V, a power of 200 mW is consumed and a single-ended swing of above 300 mV for each channel is achieved.