A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility

Tiebin WU
Hengzhu LIU

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E97-A    No.7    pp.1452-1460
Publication Date: 2014/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E97.A.1452
Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
test data compression,  block merging,  compatibility,  test application time,  code-based testing,  system-on-chip (SoC),  

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This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.