For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Design and Implement of High Performance Crypto Coprocessor
Shice NI Yong DOU Kai CHEN Jie ZHOU
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/04/01
Online ISSN: 1745-1337
Type of Manuscript: LETTER
Category: Algorithms and Data Structures
crypto coprocessor, reconfigurable crypto block, security protocol, accelerator,
Full Text: PDF(422.6KB)>>
This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.