Design and Implement of High Performance Crypto Coprocessor

Shice NI  Yong DOU  Kai CHEN  Jie ZHOU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E97-A   No.4   pp.989-990
Publication Date: 2014/04/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E97.A.989
Type of Manuscript: LETTER
Category: Algorithms and Data Structures
crypto coprocessor,  reconfigurable crypto block,  security protocol,  accelerator,  

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This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.