Leakage Power Aware Scheduling in High-Level Synthesis

Nan WANG  Song CHEN  Cong HAO  Haoran ZHANG  Takeshi YOSHIMURA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E97-A   No.4   pp.940-951
Publication Date: 2014/04/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E97.A.940
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
dual-Vth,  leakage power,  max-flow min-cut,  

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In this paper, we address the problem of scheduling operations into control steps with a dual threshold voltage (dual-Vth) technique, under timing and resource constraints. We present a two-stage algorithm for leakage power optimization. In the threshold voltage (Vth) assignment stage, the proposed algorithm first initializes all the operations to high-Vth, and then it iteratively shortens the critical path delay by reassigning the set of operations covering all the critical paths to low-Vth until the timing constraint is met. In the scheduling stage, a modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with a consideration of the resource constraints. To eliminate the potential resource constraint violations, the operations' threshold voltage adjustment problem is formulated as a “weighted interval scheduling” problem. The experimental results show that our proposed method performs better in both running time and leakage power reduction compared with MWIS [3].