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A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters
Satoshi KOMATSU Takahiro J. YAMAGUCHI Mohamed ABBAS Nguyen Ngoc MAI KHANH James TANDON Kunihiro ASADA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/03/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
flash TDC, arbiter, slope control,
Full Text: PDF(1MB)>>
This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.