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135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset
Mizuki MOTOYOSHI Naoko ONO Kosuke KATAYAMA Kyoya TAKANO Minoru FUJISHIMA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Wideband Systems)
CMOS, D-band, high-speed, wireless, ASK transceiver, short-millimeter-wave,
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An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.