A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement

Hayato MASHIKO  Yukihide KOHIRA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E97-A   No.12   pp.2443-2450
Publication Date: 2014/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E97.A.2443
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
delay variation,  timing violation,  yield,  programmable delay element,  

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Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.