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Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/11/01
Online ISSN: 1745-1337
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Post-Silicon Tunable buffer, statistical timing analysis, stochastic collocation, sparse grid,
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Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.