Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Yoshinobu HIGAMI  Hiroshi TAKAHASHI  Shin-ya KOBAYASHI  Kewal K. SALUJA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.6   pp.1323-1331
Publication Date: 2013/06/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.1323
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
test generation,  fault simulation,  clock line,  delay fault,  

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Summary: 
This paper deals with delay faults on clock lines assuming the launch-on-capture test. In this realistic fault model, the amount of delay at the FF driven by the faulty clock line is such that the scan shift operation can perform correctly even in the presence of a fault, but during the system clock operation, capturing functional value(s) at faulty FF(s), i.e. FF(s) driven by the clock with delay, is delayed and correct value(s) may not be captured. We developed a fault simulator that can handle such faults and using this simulator we investigate the relation between the duration of the delay and the difficulty of detecting clock delay faults in the launch-on-capture test. Next, we propose test generation methods for detecting clock delay faults that affect a single or two FFs. Experimental results for benchmark circuits are given in order to establish the effectiveness of the proposed methods.