Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

Wenpo ZHANG  Kazuteru NAMBA  Hideo ITO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.5   pp.1219-1222
Publication Date: 2013/05/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.1219
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Dependable Computing
Keyword: 
small delay faults,  test coverage,  flip-flop,  clock pulse,  

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Summary: 
As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.2511.28% with the same area overhead as the conventional method.