A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method

Hyuk-Jun LEE  Seung-Chul KIM  Eui-Young CHUNG  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.4   pp.963-966
Publication Date: 2013/04/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.963
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System
Keyword: 
router,  packet memory,  low power,  TCP,  

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Summary: 
A packet memory stores packets in internet routers and it requires typically RTTC for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to , where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.