Architecture and Implementation of a Reduced EPIC Processor

Jun GAO  Minxuan ZHANG  Zuocheng XING  Chaochao FENG  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.1   pp.9-18
Publication Date: 2013/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.9
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
ILP,  EPIC,  IA-64,  processor architecture,  hardware implementation,  

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Summary: 
This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm2 (1010), and consumes only 12 W power when running at 300 MHz.