Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices

Kai LIAO  XiaoXin CUI  Nan LIAO  KaiSheng MA  

IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.8   pp.1068-1075
Publication Date: 2013/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.1068
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
leakage current reduction,  adiabatic circuits,  FinFETs,  power consumption,  limiting frequency,  noise immunity,  

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With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.