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High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors Yutaka ARAYASHIKI Takashi KAMIZONO Yukio OHKUBO Taisuke MATSUMOTO Yoshiaki AMANO Yutaka MATSUOKA Publication IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.912-919 Publication Date: 2013/06/01 Online ISSN: 1745-1353 DOI: 10.1587/transele.E96.C.912 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: DHBT, MUX, DEMUX, G-CPW, module, Full Text: PDF(3.3MB)>>
Summary: We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively. | |||||
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