A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation

Toshiyuki YAMAGISHI  Tatsuo SHIOZAWA  Koji HORISAKI  Hiroyuki HARA  Yasuo UNEKAWA  

IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.6   pp.894-902
Publication Date: 2013/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.894
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
on chip,  monitor,  digital,  process variability,  standard cell,  area efficiency,  

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A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.