Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation

Satoshi TAKAYA  Yoji BANDO  Toru OHKAWA  Toshiharu TAKARAMOTO  Toshio YAMADA  Masaaki SOUDA  Shigetaka KUMASHIRO  Tohru MOGAMI  Makoto NAGATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.6   pp.884-893
Publication Date: 2013/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.884
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
mixed signal VLSI circuit,  substrate crosstalk,  on-chip noise monitoring,  

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Summary: 
The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.