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Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers
Sung-Wook JUN Lianghua MIAO Keita YASUTOMI Keiichiro KAGAWA Shoji KAWAHITO
IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
analog-to-digital conversion, digital error correction, incomplete settling error, pre-charging technique,
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This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.