A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

Masao TAKAYAMA  Shiro DOSHO  Noriaki TAKEDA  Masaya MIYAHARA  Akira MATSUZAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.6   pp.813-819
Publication Date: 2013/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.813
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
time-domain architecture,  time-to-digital converter,  interleaving,  successive approximation,  

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Summary: 
In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.