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Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress
Toshiro HIRAMOTO Anil KUMAR Takuya SARAYA Shinji MIYANO
IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
transistor, MOSFET, variability, off-state stress,
Full Text: FreePDF(3.5MB)
The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found that | VTH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.