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Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
Takeshi OKUMOTO Kumpei YOSHIKAWA Makoto NAGATA
IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
noise detection circuit, power supply noise, power supply integrity, systems-on-a-chip,
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An effective supply voltage monitor evaluates dynamic variation of (Vdd-Vss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8 14.5 µm2 and is followed by backend digitizing circuits, both using 3.3 V thick oxide transistors in a 65 nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital (shift registers) as well as in analog (4 bit Flash ADC) circuits.