An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation

Minoru IIZUKA  Naohiro HAMADA  Hiroshi SAITO  

IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.4   pp.482-491
Publication Date: 2013/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.482
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
asynchronous circuits with bundled-data implementation,  latency,  ASIC,  and design support tool,  

Full Text: PDF>>
Buy this Article

This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.