A Delay Evaluation Circuit for Analog BIST Function

Zhengliang LV  Shiyuan YANG  Hong WANG  Linda MILOR  

IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.3   pp.393-401
Publication Date: 2013/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.393
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
delay testing,  BIST,  analog filter,  sample-hold circuit,  

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Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.