Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

Chizu MATSUMOTO  Yuichi HAMAMURA  Michinobu NAKAO  Kaname YAMASAKI  Yoshikazu SAITO  Shun'ichi KANEKO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.1   pp.108-114
Publication Date: 2013/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.108
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
random access memory,  system-on-chip,  redundancy,  fuse,  

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Summary: 
Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.