A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

Li-Rong WANG  Kai-Yu LO  Shyh-Jye JOU  

IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.10   pp.1351-1355
Publication Date: 2013/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.1351
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
double-edge-triggered,  flip-flop,  level-converting,  sense amplifier,  mixed threshold voltage,  

Full Text: PDF>>
Buy this Article

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.