Improved CRC Calculation Strategies for 64-bit Serial RapidIO

Fengfeng WU  Song JIA  Qinglong MENG  Shigong LV  Yuan WANG  Dacheng ZHANG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.10   pp.1330-1338
Publication Date: 2013/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.1330
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
RapidIO,  Cyclic Redundancy Check,  embedded interconnection,  parallel CRC,  CRC slicing,  

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Summary: 
Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.