Low Power Design of Asynchronous Datapath for LDPC Decoder

XiaoBo JIANG  DeSheng YE  HongYuan LI  WenTao WU  XiangMin XU  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.9   pp.1857-1863
Publication Date: 2013/09/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.1857
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LDPC code,  asynchronous design,  low power,  adder,  comparator,  comparator-MUX,  

Full Text: PDF(2.2MB)>>
Buy this Article




Summary: 
We propose an asynchronous datapath for the low-density parity-check decoder to decrease power consumption. Glitches and redundant computations are decreased by the asynchronous design. Taking advantage of the statistical characteristics of the input data, we develop novel key arithmetic elements in the datapath to reduce redundant computations. Two other types of datapaths, including normal synchronous design and clock-gating design, are implemented for comparisons with the proposed design. The three designs use similar architectures and realize the same function by using the 0.18µm process of the Semiconductor Manufacturing International Corporation. Post-layout result shows that the proposed asynchronous design exhibits the lowest power consumption. The proposed asynchronous design saves 48.7% and 21.9% more power than the normal synchronous and clock-gating designs, respectively. The performance of the proposed datapath is slightly worse than the clock-gating design but is better than the synchronous design. The proposed design is approximately 7% larger than the other two designs.