Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

Shusuke YOSHIMOTO  Shunsuke OKUMURA  Koji NII  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.7   pp.1579-1585
Publication Date: 2013/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.1579
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Reliability, Maintainability and Safety Analysis
SRAM,  soft error rate (SER),  multiple cell upset (MCU),  neutron particle,  twin well,  triple well,  

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This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-centered 6T SRAM cells.