Intra-Gate Length Biasing for Leakage Optimization in 45 nm Technology Node

Yesung KANG  Youngmin KIM  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.5   pp.947-952
Publication Date: 2013/05/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.947
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
design for manufacturing (DFM),  leakage saving,  non-rectangular transistor,  device model,  TCAD,  gate biasing,  

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Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.