Jitter Amplifier for Oscillator-Based True Random Number Generator

Takehiko AMAKI  Masanori HASHIMOTO  Takao ONOYE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.3   pp.684-696
Publication Date: 2013/03/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.684
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Cryptography and Information Security
true random number generator,  jitter,  

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We propose a jitter amplifier architecture for an oscillator-based true random number generator (TRNG). Two types of latency-controllable (LC) buffer, which are the key components of the proposed jitter amplifier, are presented. We derive an equation to estimate the gain of the jitter amplifier, and analyze sufficient conditions for the proposed circuit to work properly. The proposed jitter amplifier was fabricated with a 65 nm CMOS process. The jitter amplifier with the two-voltage LC buffer occupied 3,300 µm2 and attained 8.4x gain, and that with the single-voltage LC buffer achieved 2.2x gain with an 1,700 µm2 area. The jitter amplification of the sampling clock increased the entropy of a bit stream and improved the results of the NIST test suite so that all the tests passed whereas TRNGs with simple correctors failed. The jitter amplifier attained higher throughput per area than a frequency divider when the required amount of jitter was more than two times larger than the inherent jitter in our test-chip implementations.