SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

Jun YAMASHITA  Hiroyuki YOTSUYANAGI  Masaki HASHIZUME  Kozo KINOSHITA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.12   pp.2561-2567
Publication Date: 2013/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.2561
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faults,  adjacent lines,  test pattern generation,  coupling capacitance,  SAT-based ATPG,  

Full Text: PDF(590.4KB)>>
Buy this Article




Summary: 
Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.