A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

Kosuke SHIMAZAKI  Shingo YOSHIZAWA  Yasuyuki HATAKAWA  Tomoko MATSUMOTO  Satoshi KONISHI  Yoshikazu MIYANAGA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E96-A   No.11   pp.2114-2119
Publication Date: 2013/11/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E96.A.2114
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: VLSI Design Technology and CAD
Keyword: 
multi-user MIMO,  Tomlinson-Harashima precoding,  LQ decomposition,  interference cancellation,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.